1. Fields of the Invention
The present invention relates to a delay locked loop circuit, especially to a clock de-skewing delay locked loop circuit.
2. Descriptions of Related Art
The quality of clock signals is one of key factors that affect circuit performance. With the continuing advance of the semiconductor process technology, the demands of chip complexity and the frequency of clock signal has both grown recently. Therefore, the quality of the clock signals in chips is getting more important. Moreover, reducing the clock skew and clock jitter has become one of important issues in the high performance very large scale integrated circuit design or System-on-Chip (SOC) design. The improved clock signal quality not only increases system operating frequency but also reduces system failure rate. Otherwise, the reliability of the chip is further improved. Along this way, the delay-locked loops (DLLs) have been widely used in improving the quality of clock signals.
A plurality of new designs has been reported to improve the performance of DLLs and the clock signal quality. The DLL can be divided into two different architectures-open loop type and close loop type. The classical designs in the open loop type are Synchronous Mirror Delay (SMD) and Clock Synchronized Delay (CSD). Under the condition that the total delay time between the input clock buffer and the output clock buffer is smaller than input clock cycle, the open loop type circuit has the advantage of fast-locking capability (phase synchronization) within two external clock cycles. Due to fast phase locking, the open loop type circuits have been used in memory circuits. However, the open loop type circuit requires dummy delay lines and clock drivers so that it has high power consumption problem. Besides the power consumption, the mismatch between the delay lines also has effect on the circuit performance.
In order to reduce power consumption, the half-delay-line de-skewing circuit (HDSC) has been developed and the circuit demands an input clock signal with a 50% duty cycle. This can be a difficult requirement because the system clock of a SoC needs to go through a large distribution network to arrive at the input terminal of the DLL, and as a consequence the duty cycle could be seriously distorted from 50%. Our analysis found that the HDSC fails to align with the clock phase if during the measurement phase, the rising edge of CK_int falls inside the pulse of CK_ext, refer to FIG. 1. After the intended delay is detected, the HDSC begins to adjust the rising edge of CK_int. However, since the phase adjuster inverts its input signal, the effective delay time becomes two times of the positive half cycle of the external clock signal CK_ext (tduty). Thus, such design is not suitable for the system in which the duty cycle of the external clock signal is not 50% and the applications of the circuit will be limited significantly.
There is a need to provide a new design of clock de-skewing delay locked loop circuit that is applied to systems in which the duty cycle of the external clock signal is not 50%. The clock de-skewing delay locked loop circuit has more applications.